Store Buffer
Updated: Oct 19th, 2023
访问内存是很慢的,读内存有cache可以优化,但写内存不好优化。
现代处理器一般会使用 “Write Buffer”,或者“Store Buffer”来隐藏写操作的延时。
! [[ Pasted image 20220608121556.png|200 ]] 图源
“Store latency has been traditionally hidden by the store buffer (SB), which allow stores to commit as long as the SB is not full. Stores are delayed in the SB while other instructions (e.g., loads) can commit, effectively relaxing the consistency model of the system (e.g., x86-TSO [25]).” (Cebrian et al., 2020, p. 568) (pdf) [1]
依托于 Write Buffer,处理器可以高效的将写内存的延迟和其他操作的延迟重叠起来,隐藏写内存的延迟。
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但是这样操作带来的问题是:写在 Store Buffer 里面的数据,只有自己可见,别的核心是不可见的,这就带来了内存序的问题:在别的 CPU 看起来,你的访存操作乱序了。
ref
- http://www.cs.cmu.edu/afs/cs/academic/class/15418-s18/www/lectures/13_consistency.pdf
[1]
J.
M. Cebrian, S. Kaxiras, and A. Ros, “Boosting Store Buffer
Efficiency with Store-Prefetch Bursts,” in 2020 53rd Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO),
2020, pp. 568–580, doi: 10.1109/MICRO50266.2020.00054.